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FP4

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RESEARCH · 1 SOURCE · arXiv cs.AI

Echo: error‑compensated 4‑bit all-reduce for tensor‑parallel LLM training and inference

The arXiv paper introduces Echo, a 4‑bit all‑reduce protocol for tensor-parallel LLM training and inference that moves 4‑bit data but sums in high precision and feeds per-call rounding errors forward so they cancel rather than accumulate. The authors prove the accumulated error is depth‑independent and report that Echo is 2.09× faster than 16‑bit NCCL all‑reduce on 1 GB messages on A100s, speeds time‑to‑first‑token and training step latency by up to ~1.16×/1.09× on idle interconnects (and larger gains under background traffic), keeps average accuracy within 0.4 points on Qwen3‑8B, and yields <0.9% higher final loss after 10B‑token pretraining — with no FP8/FP4 hardware required.

7.0

CODING · 1 SOURCE · NVIDIA Developer

Megatron Core PR #7262 adds workflow for bitwise-deterministic pretraining

Megatron-LM PR #7262 introduces a workflow and tooling in NVIDIA Megatron Core to achieve and validate bitwise-deterministic large-scale pretraining, including ordered per-rank tensor fingerprinting for offline divergence localization. Kernel-level fixes (e.g., private output slots for grouped-GEMM writers and a fixed reduction order), recipe/kernel/module validation across parallelism settings (including FP8/FP4), and optimizations on Nemotron workloads reduced the determinism overhead to about 2% at 2,432 GPUs while preserving bitwise identity over 800 steps.

7.0