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COMPANY · ENTITY #1147

HBM

Related event timeline, sources and context from the news index.

EVENT TIMELINE

6

COMPANIES · 1 SOURCE · The Decoder

Huawei reportedly tells customers to source HBM3E for Ascend 960DT on the black market

The Information reports Huawei has told some customers to procure High-Bandwidth Memory (HBM/HBM3E) themselves amid shortages and U.S. export restrictions that limit purchases from Samsung and SK Hynix. Smugglers are allegedly bundling HBM with low-end processors routed through Hong Kong, driving black‑market prices to roughly $4,000 per HBM unit and raising memory costs per Ascend 960DT chip to as much as ~$32,000.

7.0

MONEY · 1 SOURCE · Ars Technica

PC shipments plunge about 20% in Q3 2026, steepest Q3 drop on record per IDC and Omdia

Analysts report a steep decline in global PC shipments in Q3 2026: IDC says shipments fell 20.1% year‑over‑year to 62.7 million units, while Omdia reports a 21.2% drop to 58.1 million. Firms cite elevated inventory, higher component and memory prices and reduced production, with analysts linking part of the supply squeeze to surging demand for HBM and server DRAM for AI workloads.

7.0

COMPANIES · 1 SOURCE · Ars Technica

Micron, Samsung say HBM/DRAM shortage likely to continue through 2028

Micron CEO Sanjay Mehrotra told investors that demand for the company's HBM and server DRAM will exceed available supply for the next several years, with about 75% of Micron's 2027 memory already spoken for and new clean rooms only coming online in 2028. Samsung EVP Kim Taewoo likewise warned HBM wafer share will rise to about 30% in 2027, tightening DRAM capacity for consumer devices and pushing prioritization toward AI and data-center memory.

8.0

CODING · 1 SOURCE · InfoQ AI, ML & Data Engineering

Google adds cycle-level kernel profiling to XProf for TPU v7

Google added a Kernel Profiling suite to XProf (the OpenXLA/JAX profiler), exposing cycle-level details for custom kernels (e.g., Pallas) and sampling hardware performance counters on TPU v7 (Ironwood). The tooling shows lowered MLIR, per-unit time-aligned counter tracks, a Perf Counters view with ~16,000 raw counters, and supports periodic sampling (1µs floor) or external-triggered sub-microsecond capture; a Google demo using triple buffering reduced a matmul kernel from 125.5µs to 88µs.

6.0

COMPANIES · 1 SOURCE · TechCrunch AI

SK Hynix reportedly in talks with Intel to manufacture memory chips in Ohio

Reuters reports SK Hynix is discussing options with Intel to manufacture RAM/memory chips in the U.S., including leasing space at Intel’s planned Ohio fab or forming a joint venture that could involve cloud providers; SK Hynix says no decisions are finalized. The company is already building an advanced packaging facility in Indiana for HBM using DRAM wafers from Korea, and it’s unclear which memory types would be produced in Ohio if a deal proceeds.

7.0

COMPANIES · 1 SOURCE · NVIDIA Developer

NVIDIA Dynamo's Shadow Engine Recovery can restore LLM inference capacity in seconds

NVIDIA describes a Shadow Engine Recovery feature in its Dynamo system that can restore LLM inference capacity in seconds by avoiding the usual cold restart path that requires reloading weights into HBM and recompiling kernels. The feature is presented as a fast recovery mechanism for failed LLM engine processes.

7.0